A state machine diagram models the behaviour of a single object, specifying the sequence of events that an object goes through during its lifetime in response to events. As an example, the following state machine diagram shows the states that a door goes through during its lifetime. The door can be in one of three states: "Opened", "Closed" or "Locked". It can respond to the events Open, Close, Lock and Unlock. Notice that not all events are valid in all states; for example, if a door is opened, you cannot lock it until you close it. The syntax and conventions used in state machine diagrams will be discussed in full in the following sections.
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UML state machine ,  also known as UML statechart , is a significantly enhanced realization of the mathematical concept of a finite automaton in computer science applications as expressed in the Unified Modeling Language UML notation.
The concepts behind it are about organizing the way a device, computer program, or other often technical process works such that an entity or each of its sub-entities is always in exactly one of a number of possible states and where there are well-defined conditional transitions between these states.
UML statecharts introduce the new concepts of hierarchically nested states and orthogonal regions , while extending the notion of actions. UML state machines have the characteristics of both Mealy machines and Moore machines.
They support actions that depend on both the state of the system and the triggering event , as in Mealy machines, as well as entry and exit actions , which are associated with states rather than transitions, as in Moore machines. The term "UML state machine" can refer to two kinds of state machines: behavioral state machines and protocol state machines. Behavioral state machines can be used to model the behavior of individual entities e.
Protocol state machines are used to express usage protocols and can be used to specify the legal usage scenarios of classifiers, interfaces, and ports. Many software systems are event-driven , which means that they continuously wait for the occurrence of some external or internal event such as a mouse click, a button press, a time tick, or an arrival of a data packet. That's why event-driven systems are alternatively called reactive systems.
Once the event handling is complete, the system goes back to waiting for the next event. The response to an event generally depends on both the type of the event and on the internal state of the system and can include a change of state leading to a state transition. The pattern of events, states, and state transitions among those states can be abstracted and represented as a finite-state machine FSM.
The concept of a FSM is important in event-driven programming because it makes the event handling explicitly dependent on both the event-type and on the state of the system. When used correctly, a state machine can drastically cut down the number of execution paths through the code, simplify the conditions tested at each branching point, and simplify the switching between different modes of execution.
UML preserves the general form of the traditional state diagrams. The UML state diagrams are directed graphs in which nodes denote states and connectors denote state transitions. For example, Figure 1 shows a UML state diagram corresponding to the computer keyboard state machine.
In UML, states are represented as rounded rectangles labeled with state names. The transitions, represented as arrows, are labeled with the triggering events followed optionally by the list of executed actions.
The initial transition originates from the solid circle and specifies the default state when the system first begins. Every state diagram should have such a transition, which should not be labeled, since it is not triggered by an event.
The initial transition can have associated actions. An event is something that happens that affects the system. Strictly speaking, in the UML specification,  the term event refers to the type of occurrence rather than to any concrete instance of that occurrence. For example, Keystroke is an event for the keyboard, but each press of a key is not an event but a concrete instance of the Keystroke event. Another event of interest for the keyboard might be Power-on, but turning the power on tomorrow at will be just an instance of the Power-on event.
An event can have associated parameters , allowing the event instance to convey not only the occurrence of some interesting incident but also quantitative information regarding that occurrence.
For example, the Keystroke event generated by pressing a key on a computer keyboard has associated parameters that convey the character scan code as well as the status of the Shift, Ctrl, and Alt keys. An event instance outlives the instantaneous occurrence that generated it and might convey this occurrence to one or more state machines. Once generated, the event instance goes through a processing life cycle that can consist of up to three stages.
First, the event instance is received when it is accepted and waiting for processing e. Later, the event instance is dispatched to the state machine, at which point it becomes the current event. Finally, it is consumed when the state machine finishes processing the event instance. A consumed event instance is no longer available for processing. Each state machine has a state , which governs reaction of the state machine to events.
For example, when you strike a key on a keyboard, the character code generated will be either an uppercase or a lowercase character, depending on whether the Caps Lock is active.
The behavior of a keyboard depends only on certain aspects of its history, namely whether the Caps Lock key has been pressed, but not, for example, on how many and exactly which other keys have been pressed previously. A state can abstract away all possible but irrelevant event sequences and capture only the relevant ones. In the context of software state machines and especially classical FSMs , the term state is often understood as a single state variable that can assume only a limited number of a priori determined values e.
The idea of state variable and classical FSM model is that the value of the state variable fully defines the current state of the system at any given time. The concept of the state reduces the problem of identifying the execution context in the code to testing just the state variable instead of many variables, thus eliminating a lot of conditional logic.
In practice, however, interpreting the whole state of the state machine as a single state variable quickly becomes impractical for all state machines beyond very simple ones. Indeed, even if we have a single bit integer in our machine state, it could contribute to over 4 billion different states - and will lead to a premature state explosion.
This interpretation is not practical, so in UML state machines the whole state of the state machine is commonly split into a enumeratable state variable and b all the other variables which are named extended state. Another way to see it is to interpret enumeratable state variable as a qualitative aspect and extended state as quantitative aspects of the whole state. In this interpretation, a change of variable does not always imply a change of the qualitative aspects of the system behavior and therefore does not lead to a change of state.
State machines supplemented with extended state variables are called extended state machines and UML state machines belong to this category.
Extended state machines can apply the underlying formalism to much more complex problems than is practical without including extended state variables. The state diagram from Figure 2 is an example of an extended state machine, in which the complete condition of the system called the extended state is the combination of a qualitative aspect—the state variable —and the quantitative aspects—the extended state variables.
The obvious advantage of extended state machines is flexibility. This flexibility of extended state machines comes with a price, however, because of the complex coupling between the "qualitative" and the "quantitative" aspects of the extended state. The coupling occurs through the guard conditions attached to transitions, as shown in Figure 2. Guard conditions or simply guards are Boolean expressions evaluated dynamically based on the value of extended state variables and event parameters. Guard conditions affect the behavior of a state machine by enabling actions or transitions only when they evaluate to TRUE and disabling them when they evaluate to FALSE.
In the UML notation, guard conditions are shown in square brackets e. The need for guards is the immediate consequence of adding memory extended state variables to the state machine formalism.
Used sparingly, extended state variables and guards make up a powerful mechanism that can simplify designs. On the other hand, it is possible to abuse extended states and guards quite easily.
Any parameter values associated with the current event are available to all actions directly caused by that event. Switching from one state to another is called state transition , and the event that causes it is called the triggering event, or simply the trigger. In both cases, pressing CapsLock is the triggering event. In extended state machines , a transition can have a guard , which means that the transition can "fire" only if the guard evaluates to TRUE.
A state can have many transitions in response to the same trigger, as long as they have nonoverlapping guards; however, this situation could create problems in the sequence of evaluation of the guards when the common trigger occurs.
The UML specification  intentionally does not stipulate any particular order; rather, UML puts the burden on the designer to devise guards in such a way that the order of their evaluation does not matter. Practically, this means that guard expressions should have no side effects, at least none that would alter evaluation of other guards having the same trigger.
All state machine formalisms, including UML state machines, universally assume that a state machine completes processing of each event before it can start processing the next event.
This model of execution is called run to completion , or RTC. New incoming events cannot interrupt the processing of the current event and must be stored typically in an event queue until the state machine becomes idle again. These semantics completely avoid any internal concurrency issues within a single state machine. The RTC model also gets around the conceptual problem of processing actions associated with transitions, where the state machine is not in a well-defined state is between two states for the duration of the action.
During event processing, the system is unresponsive unobservable , so the ill-defined state during that time has no practical significance. In a multitasking environment , other tasks not related to the task context of the busy state machine can be running, possibly preempting the currently executing state machine. As long as other state machines do not share variables or other resources with each other, there are no concurrency hazards. The key advantage of RTC processing is simplicity.
Its biggest disadvantage is that the responsiveness of a state machine is determined by its longest RTC step. Achieving short RTC steps can often significantly complicate real-time designs.
Though the traditional FSMs are an excellent tool for tackling smaller problems, it's also generally known that they tend to become unmanageable, even for moderately involved systems. Due to the phenomenon known as state and transition explosion , the complexity of a traditional FSM tends to grow much faster than the complexity of the system it describes.
This happens because the traditional state machine formalism inflicts repetitions. For example, if you try to represent the behavior of a simple pocket calculator with a traditional FSM, you'll immediately notice that many events e. A conventional FSM shown in the figure below, has no means of capturing such a commonality and requires repeating the same actions and transitions in many states.
What's missing in the traditional state machines is the mechanism for factoring out the common behavior in order to share it across many states.
They provide a number of features for eliminating the repetitions so that the complexity of a UML state machine no longer explodes but tends to faithfully represent the complexity of the reactive system it describes.
Obviously, these features are very interesting to software developers, because only they make the whole state machine approach truly applicable to real-life problems.
The most important innovation of UML state machines over the traditional FSMs is the introduction of hierarchically nested states that is why statecharts are also called hierarchical state machines , or HSM s. The semantics associated with state nesting are as follows see Figure 3 : If a system is in the nested state, for example "result" called the substate , it also implicitly is in the surrounding state "on" called the superstate. This state machine will attempt to handle any event in the context of the substate, which conceptually is at the lower level of the hierarchy.
However, if the substate "result" does not prescribe how to handle the event, the event is not quietly discarded as in a traditional "flat" state machine; rather, it is automatically handled at the higher level context of the superstate "on".
This is what is meant by the system being in state "result" as well as "on". Of course, state nesting is not limited to one level only, and the simple rule of event processing applies recursively to any level of nesting. States that contain other states are called composite states ; conversely, states without internal structure are called simple states.
A nested state is called a direct substate when it is not contained by any other state; otherwise, it is referred to as a transitively nested substate. Because the internal structure of a composite state can be arbitrarily complex, any hierarchical state machine can be viewed as an internal structure of some higher-level composite state.
It is conceptually convenient to define one composite state as the ultimate root of state machine hierarchy. In the UML specification,  every state machine has a top state the abstract root of every state machine hierarchy , which contains all the other elements of the entire state machine. The graphical rendering of this all-enclosing top state is optional. As you can see, the semantics of hierarchical state decomposition are designed to facilitate reusing of behavior. The substates nested states need only define the differences from the superstates containing states.
UML state machine
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